the United States’s
chip design and eda industry,
in focus.

Physical Design and Lithography Challenges

22.2% of this theme group

Researchers highlight difficulties in placement, routing, and lithography for very‑large‑scale integration.

Physical design (38) · Routing (11) · Lithography (8) · Very-large-scale integration (11)

Advancing Placement

Interactive physical design tuning

Automation Limits in EDA Systems

19.8% of this theme group

Papers discuss constraints and gaps in current electronic design automation and systems engineering tools.

Automation (50) · Electronic design automation (56) · Systems engineering (9) · Domain (4)

Opportunities for Machine Learning in Electronic Design Automation

Genetic design automation

Circuit and IC Design Variability Issues

16.8% of this theme group

Works point out variability, statistical concerns, and scaling problems in analog and digital IC design.

Circuit design (17) · Integrated circuit design (15) · Node (10) · Chip (9)

Analog Circuit Design in Nanoscale CMOS Technologies

Variability and Statistical Design

EDA Education and Many‑core Integration

15.6% of this theme group

Studies flag the need for better training and the impact of many‑core processors on design automation.

Electronic design automation (36) · Automation (20) · Engineering management (6) · Enhanced Data Rates for GSM Evolution (5)

“Scaling” the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automa

Reinventing EDA with manycore processors

Logic Synthesis and Gate‑Level Optimization

12.3% of this theme group

Authors note challenges in reducing logic complexity and improving synthesis techniques for pass‑transistor logic.

Logic gate (28) · Logic synthesis (15) · Electronic circuit (9) · Pass transistor logic (5)

A Framework for Genetic Logic Synthesis

Features Reduction Using Logic Minimization Techniques

FPGA Design and Teaching Gaps

7.8% of this theme group

Papers identify shortcomings in FPGA‑centric curricula and integration of digital design with assembly programming.

Field-programmable gate array (22) · Programmable logic device (6) · Logic synthesis (7) · Register-transfer level (4)

Integrating digital logic design and assembly programming using FPGAs in the classroom

Teaching Field Programmable Gate Array Design (Fpga) To Future Electrical Engineering Technologists: Course Development

3‑D IC Floorplanning and Interconnect Bottlenecks

5.7% of this theme group

Research points to bandwidth and interconnection hurdles in three‑dimensional integrated circuit layouts.

Three-dimensional integrated circuit (9) · Floorplan (5) · Bandwidth (2) · Interconnection (3)

Design space exploration for 3D integrated circuits

Design Automation and Test Solutions for Monolithic 3D ICs

Through‑Silicon‑Via Management Risks

28.6% of this theme group

Authors caution about timing and density decisions for TSV insertion during 3‑D physical design.

Physical design (6) · Interconnection (6) · Power (4) · Through-silicon via (3)

Through-silicon-via management during 3D physical design: When to add and how many?

Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper)

Power Overheads in Emerging Logic Styles

27.3% of this theme group

Studies warn of increased power and area costs when using pass‑transistor and memristor‑based logic.

Logic gate (13) · Pass transistor logic (5) · CMOS (6) · Logic synthesis (6)

Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods

Overhead Requirements for Stateful Memristor Logic

Automation Accuracy for Optical NoCs and Power Measurement

23.4% of this theme group

Papers advise careful validation of routing tools and power‑analysis methods in emerging network‑on‑chip designs.

Automation (8) · Electronic design automation (7) · Reuse (2) · Routing (3)

Wavelength-Routed Optical NoCs: Design and EDA — State of the Art and Future Directions: Invited Paper

TECHNIQUE FOR ACCURATE POWER AND ENERGY MEASUREMENT WITH THE COMPUTER-AIDED DESIGN TOOLS

High‑Level Synthesis Security and Flow Complexity

20.8% of this theme group

Works highlight hardware Trojan risks and the intricacy of integrating HLS into existing design flows.

High-level synthesis (4) · Design flow (5) · Register-transfer level (3) · Hardware Trojan (2)

Fast and effective placement and routing directed high-level synthesis for FPGAs

PDL: a high-level hardware design language for pipelined processors

Integrated Physical and Circuit Design Exploration

21.6% of this theme group

Opportunities focus on systematic analog design and cost‑aware exploration of 3‑D IC architectures.

Physical design (164) · Design flow (120) · Circuit design (67) · Integrated circuit design (62)

Systematic Design of Analog CMOS Circuits

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)

Scalable Routing and Placement Techniques

18.9% of this theme group

Research proposes methods to improve routability and placement efficiency for large‑scale mixed‑size designs.

Routing (93) · Netlist (68) · Very-large-scale integration (50) · Scalability (52)

Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs

Optimizing routability in large-scale mixed-size placement

Novel Logic Families and Nano‑Scale Gates

16.9% of this theme group

Papers present new pass‑transistor and nano‑thermo‑mechanical logic concepts for future gate designs.

Logic gate (430) · Pass transistor logic (159) · Logic family (122) · NAND gate (63)

mLogic

NanoThermoMechanical AND and OR Logic Gates

Automation for 3‑D and Flexible Electronics

14.9% of this theme group

Studies explore CAD tools and process kits enabling design of three‑dimensional and hybrid flexible circuits.

Automation (192) · Electronic design automation (223) · Systems engineering (23) · Manufacturing engineering (16)

Design and CAD for 3D integrated circuits

Process design kit and design automation for flexible hybrid electronics

Approximate Logic Synthesis Advances

14.6% of this theme group

Works demonstrate statistical certification and optimization techniques for approximate circuit synthesis.

Logic synthesis (229) · Logic gate (235) · Logic optimization (68) · Sequential logic (62)

Statistically certified approximate logic synthesis

Logic Synthesis of Approximate Circuits

FPGA‑Based Embedded System Innovations

10.9% of this theme group

Research highlights heterogeneous FPGA architectures and embedded designs improving area, power, and performance.

Field-programmable gate array (277) · Programmable logic array (32) · Lookup table (36) · Embedded system (60)

FPGA-based embedded system design

Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance

Adiabatic and Energy‑Efficient Computing

2.3% of this theme group

Papers investigate ultra‑low‑power adiabatic circuits and processors for next‑generation energy‑constrained systems.

Adiabatic circuit (51) · Adiabatic process (29) · CMOS (26) · Logic gate (38)

Adiabatic Quantum-Flux-Parametron: Towards Building Extremely Energy-Efficient Circuits and Systems

A Mini-MIPS microprocessor for adiabatic computing

San Jose

24.0% across the displayed hubs

6 companies hiring · $4.7B disclosed funding

Santa Clara

20.7% across the displayed hubs

9 companies hiring · $3.3B disclosed funding

Sunnyvale

15.9% across the displayed hubs

6 companies hiring · $7.1B disclosed funding

San Diego

9.6% across the displayed hubs

3 companies hiring · $1.0B disclosed funding

Austin

8.5% across the displayed hubs

3 companies hiring · $1.2B disclosed funding

San Francisco

7.7% across the displayed hubs

3 companies hiring · $365.9M disclosed funding

Milpitas

7.7% across the displayed hubs

2 companies hiring · $187.2M disclosed funding

Mountain View

5.9% across the displayed hubs

1 companies hiring · $245.2M disclosed funding